/openbmc/linux/drivers/platform/x86/intel/pmc/ |
H A D | Kconfig | 22 - MPHY/PLL gating status (Sunrisepoint PCH only)
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | amlogic,a1-pll-clkc.yaml | 7 title: Amlogic A1 PLL Clock Control Unit
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H A D | ti,cdce706.txt | 1 Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
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H A D | allwinner,sun4i-a10-pll1-clk.yaml | 7 title: Allwinner A10 CPU PLL
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H A D | nuvoton,ma35d1-clk.yaml | 36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
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H A D | qcom,gcc-qcs404.yaml | 30 - description: HDMI phy PLL clock
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H A D | imx6sll-clock.yaml | 22 interrupt for oscillator read or PLL lock.
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H A D | imx5-clock.yaml | 30 interrupt for oscillator read or PLL lock.
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H A D | qcom,ipq9574-gcc.yaml | 29 - description: Bias PLL ubi clock source
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H A D | imx6ul-clock.yaml | 22 interrupt for oscillator read or PLL lock.
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H A D | imx6sx-clock.yaml | 22 interrupt for oscillator read or PLL lock.
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/openbmc/linux/drivers/clk/rockchip/ |
H A D | clk-rk3328.c | 215 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p, 218 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p, 221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p, 224 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p, 227 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
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H A D | clk-rk3036.c | 137 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 139 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4), 141 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
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H A D | clk-rk3228.c | 169 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0), 171 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3), 173 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6), 175 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
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/openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/ |
H A D | CP00.interface.yaml | 43 The "#P" keyword.PLL Overrides.
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/openbmc/linux/Documentation/devicetree/bindings/display/ |
H A D | amlogic,meson-vpu.yaml | 19 D |-------| |----| | | | | HDMI PLL | 53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
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/openbmc/linux/Documentation/devicetree/bindings/phy/ |
H A D | rockchip,px30-dsi-dphy.yaml | 29 - description: PLL reference clock
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H A D | bcm-ns-usb2-phy.yaml | 10 To initialize USB 2.0 PHY driver needs to setup PLL correctly.
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H A D | qcom,edp-phy.yaml | 30 - description: PLL register block
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/openbmc/linux/Documentation/driver-api/thermal/ |
H A D | intel_dptf.rst | 285 Current DLVR PLL frequency in MHz. 288 Sets DLVR PLL clock frequency. Once set, and enabled via 290 DLVR PLL frequency. 293 PLL can't accept frequency change when set.
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/openbmc/linux/Documentation/gpu/ |
H A D | meson.rst | 18 D |-------| |----| | | | | HDMI PLL |
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/openbmc/linux/Documentation/devicetree/bindings/perf/ |
H A D | amlogic,g12-ddr-pmu.yaml | 28 - description: DMC PLL register space.
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/openbmc/linux/Documentation/userspace-api/media/v4l/ |
H A D | ext-ctrls-rf-tuner.rst | 16 called Zero-IF tuners. Older tuners were typically simple PLL tuners 88 Is synthesizer PLL locked? RF tuner is receiving given frequency
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/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/ |
H A D | aiutils.h | 104 #define PLL 0x2 /* main chip pll */ macro
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/openbmc/linux/arch/arm64/boot/dts/qcom/ |
H A D | msm8956-sony-xperia-loire.dtsi | 93 /* Set always on until the CPU PLL is done */ 118 /* Set always on until the CPU PLL is done */
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