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Searched refs:PLL (Results 126 – 150 of 294) sorted by relevance

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/openbmc/linux/drivers/platform/x86/intel/pmc/
H A DKconfig22 - MPHY/PLL gating status (Sunrisepoint PCH only)
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Damlogic,a1-pll-clkc.yaml7 title: Amlogic A1 PLL Clock Control Unit
H A Dti,cdce706.txt1 Bindings for Texas Instruments CDCE706 programmable 3-PLL clock
H A Dallwinner,sun4i-a10-pll1-clk.yaml7 title: Allwinner A10 CPU PLL
H A Dnuvoton,ma35d1-clk.yaml36 A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
H A Dqcom,gcc-qcs404.yaml30 - description: HDMI phy PLL clock
H A Dimx6sll-clock.yaml22 interrupt for oscillator read or PLL lock.
H A Dimx5-clock.yaml30 interrupt for oscillator read or PLL lock.
H A Dqcom,ipq9574-gcc.yaml29 - description: Bias PLL ubi clock source
H A Dimx6ul-clock.yaml22 interrupt for oscillator read or PLL lock.
H A Dimx6sx-clock.yaml22 interrupt for oscillator read or PLL lock.
/openbmc/linux/drivers/clk/rockchip/
H A Dclk-rk3328.c215 [apll] = PLL(pll_rk3328, PLL_APLL, "apll", mux_pll_p,
218 [dpll] = PLL(pll_rk3328, PLL_DPLL, "dpll", mux_pll_p,
221 [cpll] = PLL(pll_rk3328, PLL_CPLL, "cpll", mux_pll_p,
224 [gpll] = PLL(pll_rk3328, PLL_GPLL, "gpll", mux_pll_p,
227 [npll] = PLL(pll_rk3328, PLL_NPLL, "npll", mux_pll_p,
H A Dclk-rk3036.c137 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
139 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(4),
141 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
H A Dclk-rk3228.c169 [apll] = PLL(pll_rk3036, PLL_APLL, "apll", mux_pll_p, 0, RK2928_PLL_CON(0),
171 [dpll] = PLL(pll_rk3036, PLL_DPLL, "dpll", mux_pll_p, 0, RK2928_PLL_CON(3),
173 [cpll] = PLL(pll_rk3036, PLL_CPLL, "cpll", mux_pll_p, 0, RK2928_PLL_CON(6),
175 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
/openbmc/phosphor-dbus-interfaces/yaml/com/ibm/ipzvpd/
H A DCP00.interface.yaml43 The "#P" keyword.PLL Overrides.
/openbmc/linux/Documentation/devicetree/bindings/display/
H A Damlogic,meson-vpu.yaml19 D |-------| |----| | | | | HDMI PLL |
53 The VENC Unit gets a Pixel Clocks (VCLK) from a dedicated HDMI PLL and clock
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Drockchip,px30-dsi-dphy.yaml29 - description: PLL reference clock
H A Dbcm-ns-usb2-phy.yaml10 To initialize USB 2.0 PHY driver needs to setup PLL correctly.
H A Dqcom,edp-phy.yaml30 - description: PLL register block
/openbmc/linux/Documentation/driver-api/thermal/
H A Dintel_dptf.rst285 Current DLVR PLL frequency in MHz.
288 Sets DLVR PLL clock frequency. Once set, and enabled via
290 DLVR PLL frequency.
293 PLL can't accept frequency change when set.
/openbmc/linux/Documentation/gpu/
H A Dmeson.rst18 D |-------| |----| | | | | HDMI PLL |
/openbmc/linux/Documentation/devicetree/bindings/perf/
H A Damlogic,g12-ddr-pmu.yaml28 - description: DMC PLL register space.
/openbmc/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-rf-tuner.rst16 called Zero-IF tuners. Older tuners were typically simple PLL tuners
88 Is synthesizer PLL locked? RF tuner is receiving given frequency
/openbmc/linux/drivers/net/wireless/broadcom/brcm80211/brcmsmac/
H A Daiutils.h104 #define PLL 0x2 /* main chip pll */ macro
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8956-sony-xperia-loire.dtsi93 /* Set always on until the CPU PLL is done */
118 /* Set always on until the CPU PLL is done */

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