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Searched refs:HWADDR_PRIx (Results 76 – 100 of 208) sorted by relevance

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/openbmc/qemu/hw/intc/
H A Dgoldfish_pic.c90 "%s: unimplemented register read 0x%02"HWADDR_PRIx"\n", in goldfish_pic_read()
120 "%s: unimplemented register write 0x%02"HWADDR_PRIx"\n", in goldfish_pic_write()
H A Dloongson_liointc.c150 qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", in liointc_read()
162 qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", in liointc_write()
H A Dbcm2835_ic.c128 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", in bcm2835_ic_read()
165 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", in bcm2835_ic_write()
/openbmc/qemu/hw/misc/
H A Daspeed_i3c.c153 "%s: write to readonly register[0x%02" HWADDR_PRIx in aspeed_i3c_device_write()
235 "%s: Unsupported I2C mode [0x%08" HWADDR_PRIx in aspeed_i3c_write()
242 "%s: Unsupported slave mode [%08" HWADDR_PRIx in aspeed_i3c_write()
H A Dstm32l4x5_syscfg.c129 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); in stm32l4x5_syscfg_read()
201 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); in stm32l4x5_syscfg_write()
H A Dimx7_src.c115 HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); in imx7_src_read()
177 HWADDR_PRIx "\n", TYPE_IMX7_SRC, __func__, offset); in imx7_src_write()
H A Dimx25_ccm.c238 HWADDR_PRIx "\n", TYPE_IMX25_CCM, __func__, offset); in imx25_ccm_read()
263 HWADDR_PRIx "\n", TYPE_IMX25_CCM, __func__, offset); in imx25_ccm_write()
H A Dnrf51_rng.c55 "%s: bad read offset 0x%" HWADDR_PRIx "\n", in rng_read()
133 "%s: bad write offset 0x%" HWADDR_PRIx "\n", in rng_write()
H A Dmips_cmgcr.c113 qemu_log_mask(LOG_UNIMP, "Read %d bytes at GCR offset 0x%" HWADDR_PRIx in gcr_read()
164 qemu_log_mask(LOG_UNIMP, "Write %d bytes at GCR offset 0x%" HWADDR_PRIx in gcr_write()
H A Dimx6_src.c110 HWADDR_PRIx "\n", TYPE_IMX6_SRC, __func__, offset); in imx6_src_read()
172 HWADDR_PRIx "\n", TYPE_IMX6_SRC, __func__, offset); in imx6_src_write()
H A Dzynq_slcr.c512 " addr %" HWADDR_PRIx "\n", offset * 4); in zynq_slcr_read()
515 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx32 "\n", offset * 4, ret); in zynq_slcr_read()
525 DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4, val); in zynq_slcr_write()
529 "addr %" HWADDR_PRIx "\n", offset * 4); in zynq_slcr_write()
/openbmc/qemu/hw/fsi/
H A Daspeed_apb2opb.c104 "%s: Out of bounds read: 0x%"HWADDR_PRIx" for %u\n", in fsi_aspeed_apb2opb_read()
160 "%s: Out of bounds write: %"HWADDR_PRIx" for %u\n", in fsi_aspeed_apb2opb_write()
220 "%s: Invalid operation: 0x%"HWADDR_PRIx" for %u\n", in fsi_aspeed_apb2opb_write()
/openbmc/qemu/hw/vfio/
H A Dspapr.c314 error_report("Host doesn't support DMA window at %"HWADDR_PRIx", must be %"PRIx64, in vfio_spapr_create_window()
354 " 0x%"HWADDR_PRIx"..0x%"HWADDR_PRIx, container, in vfio_spapr_container_add_section_window()
440 hw_error("%s: Cannot delete missing window at %"HWADDR_PRIx, in vfio_spapr_container_del_section_window()
/openbmc/qemu/hw/net/
H A Dnpcm7xx_emc.c217 HWADDR_PRIx "\n", __func__, addr); in emc_read_tx_desc()
238 HWADDR_PRIx "\n", __func__, addr); in emc_write_tx_desc()
249 HWADDR_PRIx "\n", __func__, addr); in emc_read_rx_desc()
270 HWADDR_PRIx "\n", __func__, addr); in emc_write_rx_desc()
625 "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", in npcm7xx_emc_read()
665 "%s: Invalid offset 0x%04" HWADDR_PRIx "\n", in npcm7xx_emc_write()
H A Dnpcm_gmac.c215 HWADDR_PRIx "\n", __func__, addr); in gmac_read_rx_desc()
235 HWADDR_PRIx "\n", __func__, addr); in gmac_write_rx_desc()
246 HWADDR_PRIx "\n", __func__, addr); in gmac_read_tx_desc()
266 HWADDR_PRIx "\n", __func__, addr); in gmac_write_tx_desc()
711 "%s: Read of write-only reg: offset: 0x%04" HWADDR_PRIx in npcm_gmac_read()
744 "%s: Write of read-only reg: offset: 0x%04" HWADDR_PRIx in npcm_gmac_write()
824 HWADDR_PRIx ", value: 0x%04" PRIx64 "\n", in npcm_gmac_write()
/openbmc/qemu/hw/sd/
H A Daspeed_sdhci.c59 "%s: Out-of-bounds read at 0x%" HWADDR_PRIx "\n", in aspeed_sdhci_read()
98 "%s: Out-of-bounds write at 0x%" HWADDR_PRIx "\n", in aspeed_sdhci_write()
/openbmc/qemu/hw/pci-host/
H A Dpnv_phb3_pbcq.c160 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_nest_xscom_write()
177 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_pci_xscom_write()
203 phb3_pbcq_error(pbcq, "%s @0x%"HWADDR_PRIx"=%"PRIx64, __func__, in pnv_pbcq_spci_xscom_write()
/openbmc/qemu/hw/i2c/
H A Dbcm2835_i2c.c129 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); in bcm2835_i2c_read()
205 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); in bcm2835_i2c_write()
H A Dnpcm7xx_smbus.c743 "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_read()
804 "%s: read from invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_read()
861 "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
871 "%s: write to read-only reg: offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
910 "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
971 "%s: write to invalid offset 0x%" HWADDR_PRIx "\n", in npcm7xx_smbus_write()
/openbmc/qemu/hw/char/
H A Dbcm2835_aux.c151 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", in bcm2835_aux_read()
213 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", in bcm2835_aux_write()
H A Dgoldfish_tty.c60 "%s: unimplemented register read 0x%02"HWADDR_PRIx"\n", in goldfish_tty_read()
153 "%s: unimplemented register write 0x%02"HWADDR_PRIx"\n", in goldfish_tty_write()
/openbmc/qemu/hw/ppc/
H A Dpnv_xscom.c166 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba); in xscom_read()
192 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n", in xscom_write()
/openbmc/qemu/hw/arm/
H A Dpxa2xx.c122 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", in pxa2xx_pm_read()
155 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", in pxa2xx_pm_write()
198 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", in pxa2xx_cm_read()
225 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", in pxa2xx_cm_write()
431 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", in pxa2xx_mm_read()
452 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", in pxa2xx_mm_write()
660 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", in pxa2xx_ssp_read()
754 "%s: Bad write offset 0x%"HWADDR_PRIx"\n", in pxa2xx_ssp_write()
1017 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", in pxa2xx_rtc_read()
1377 "%s: Bad read offset 0x%"HWADDR_PRIx"\n", in pxa2xx_i2c_read()
[all …]
/openbmc/qemu/hw/ssi/
H A Dbcm2835_spi.c134 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); in bcm2835_spi_read()
213 "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, addr); in bcm2835_spi_write()
/openbmc/qemu/hw/timer/
H A Dpxa2xx_timer.c261 "%s: unknown register 0x%02" HWADDR_PRIx "\n", in pxa2xx_timer_read()
266 "%s: incorrect register 0x%02" HWADDR_PRIx "\n", in pxa2xx_timer_read()
392 "%s: unknown register 0x%02" HWADDR_PRIx " " in pxa2xx_timer_write()
397 "%s: incorrect register 0x%02" HWADDR_PRIx " " in pxa2xx_timer_write()

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