Searched refs:BAR (Results 51 – 57 of 57) sorted by relevance
123
25 namespace [2]. The _CRS is like a generalized PCI BAR: the OS can read
149 This adds a Controller Memory Buffer of the given size at offset zero in BAR
27 - BAR mapped memory accesses used for registers and mailboxes.
143 device memory BAR, which is mapped with write-combine capability.
772 39 SPACE BAR
3609 +�С� #JN BAR
4472 can resize a BAR to allow access to all VRAM.