Searched refs:BANK_SELECT (Results 26 – 37 of 37) sorted by relevance
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| /openbmc/linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mmhub_v9_4.c | 235 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12); in mmhub_v9_4_init_cache_regs()
239 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9); in mmhub_v9_4_init_cache_regs()
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| H A D | gmc_v7_0.c | 643 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v7_0_gart_enable()
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| H A D | sid.h | 387 #define BANK_SELECT(x) ((x) << 0) macro
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| H A D | gmc_v8_0.c | 859 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, field); in gmc_v8_0_gart_enable()
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| /openbmc/linux/drivers/gpu/drm/radeon/ |
| H A D | nid.h | 121 #define BANK_SELECT(x) ((x) << 0) macro
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| H A D | sid.h | 386 #define BANK_SELECT(x) ((x) << 0) macro
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| H A D | cikd.h | 504 #define BANK_SELECT(x) ((x) << 0) macro
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| H A D | evergreen.c | 2416 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_enable()
2469 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_pcie_gart_disable()
2499 WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); in evergreen_agp_enable()
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| H A D | evergreend.h | 1159 #define BANK_SELECT(x) ((x) << 0) macro
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| H A D | ni.c | 1289 BANK_SELECT(6) | in cayman_pcie_gart_enable()
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| H A D | si.c | 4312 BANK_SELECT(4) | in si_pcie_gart_enable()
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| H A D | cik.c | 5447 BANK_SELECT(4) | in cik_pcie_gart_enable()
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