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H A D | ipu-image-convert.c | ff652fcf Tue Sep 18 04:34:17 CDT 2018 Philipp Zabel <p.zabel@pengutronix.de> gpu: ipu-v3: image-convert: relax alignment restrictions
For the planar but U/V-packed formats NV12 and NV16, 8 pixel width alignment is good enough to fulfill the 8 byte stride requirement. If we allow the input 8-pixel DMA bursts to overshoot the end of the line, the only input alignment restrictions are dictated by the pixel format and 8-byte aligned line start address. Since different tile sizes are allowed, the output tile with / height alignment doesn't need to be multiplied by number of columns / rows.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [slongerbeam@gmail.com: Bring in the fixes to format width and height alignment restrictions from imx-media-mem2mem.c.] Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> ff652fcf Tue Sep 18 04:34:17 CDT 2018 Philipp Zabel <p.zabel@pengutronix.de> gpu: ipu-v3: image-convert: relax alignment restrictions For the planar but U/V-packed formats NV12 and NV16, 8 pixel width alignment is good enough to fulfill the 8 byte stride requirement. If we allow the input 8-pixel DMA bursts to overshoot the end of the line, the only input alignment restrictions are dictated by the pixel format and 8-byte aligned line start address. Since different tile sizes are allowed, the output tile with / height alignment doesn't need to be multiplied by number of columns / rows. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> [slongerbeam@gmail.com: Bring in the fixes to format width and height alignment restrictions from imx-media-mem2mem.c.] Signed-off-by: Steve Longerbeam <slongerbeam@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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