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| H A D | engleder,tsnep.yaml | ff46c610 Tue Sep 27 14:58:37 CDT 2022 Gerhard Engleder <gerhard@engleder-embedded.com> dt-bindings: net: tsnep: Allow dma-coherent
Within SoCs like ZynqMP, FPGA logic can be connected to different kinds
of AXI master ports. Also cache coherent AXI master ports are available.
The property "dma-coherent" is used to signal that DMA is cache
coherent.
Add "dma-coherent" property to allow the configuration of cache coherent
DMA.
Signed-off-by: Gerhard Engleder <gerhard@engleder-embedded.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
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