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/openbmc/u-boot/drivers/clk/at91/
H A DMakefilefed0509c Thu Feb 08 21:34:51 CST 2018 Wenyou Yang <wenyou.yang@microchip.com> clk: at91: add PLLADIV driver

As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
H A Dclk-plladiv.cfed0509c Thu Feb 08 21:34:51 CST 2018 Wenyou Yang <wenyou.yang@microchip.com> clk: at91: add PLLADIV driver

As said in the SAMA5D2 datasheet, the PLLA clock must be divided
by 2 by writing the PLLADIV2 bit in PMC_MCKR, if the ratio between
PCK and MCK is 3 (MDIV = 3). This is the purpose of the driver.

Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>