Searched hist:fe3fbd30 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/include/configs/ |
| H A D | bayleybay.h | fe3fbd30 Thu Jul 30 05:49:18 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| /openbmc/u-boot/arch/x86/cpu/baytrail/ |
| H A D | valleyview.c | fe3fbd30 Thu Jul 30 05:49:18 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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| /openbmc/u-boot/arch/x86/dts/ |
| H A D | bayleybay.dts | fe3fbd30 Thu Jul 30 05:49:18 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
|
| /openbmc/u-boot/configs/ |
| H A D | bayleybay_defconfig | fe3fbd30 Thu Jul 30 05:49:18 CDT 2015 Bin Meng <bmeng.cn@gmail.com> x86: bayleybay: Configure PCI IRQ
Add PCI IRQ routing information in the board device tree and enable
writing PIRQ routing table and MP table.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
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