Searched hist:f7cf291a (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-at91/ |
| H A D | atmel_sfr.c | f7cf291a Tue Feb 16 02:45:06 CST 2016 Samuel Mescoff <samuel.mescoff@mobile-devices.fr> ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
| H A D | spl_atmel.c | f7cf291a Tue Feb 16 02:45:06 CST 2016 Samuel Mescoff <samuel.mescoff@mobile-devices.fr> ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
| /openbmc/u-boot/arch/arm/mach-at91/include/mach/ |
| H A D | at91_common.h | f7cf291a Tue Feb 16 02:45:06 CST 2016 Samuel Mescoff <samuel.mescoff@mobile-devices.fr> ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
|
| H A D | sama5_sfr.h | f7cf291a Tue Feb 16 02:45:06 CST 2016 Samuel Mescoff <samuel.mescoff@mobile-devices.fr> ARM: at91: sama5d2: configure the L2 cache memory
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2
cache memory.
Make sure it is configured as a L2 cache memory when booting from a SPL
image.
Based on the commit b5ea95ef2b5b from the at91bootstrap repository.
Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr>
Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com>
Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
|