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| /openbmc/linux/arch/arm64/boot/dts/renesas/ |
| H A D | r8a779g0.dtsi | f0840721 Mon Nov 14 06:49:00 CST 2022 Geert Uytterhoeven <geert+renesas@glider.be> arm64: dts: renesas: r8a779g0: Add L3 cache controller
Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.
Extracted from a larger patch in the BSP by Takeshi Kihara.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
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