Searched hist:ebe4c1e6 (Results 1 – 4 of 4) sorted by relevance
/openbmc/u-boot/arch/arm/include/asm/arch-ls102xa/ |
H A D | immap_ls102xa.h | ebe4c1e6 Wed Aug 12 05:29:14 CDT 2015 Claudiu Manoil <claudiu.manoil@freescale.com> ls102xa: etsec: Use proper settings for BE BDs Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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/openbmc/u-boot/board/freescale/ls1021aqds/ |
H A D | ls1021aqds.c | ebe4c1e6 Wed Aug 12 05:29:14 CDT 2015 Claudiu Manoil <claudiu.manoil@freescale.com> ls102xa: etsec: Use proper settings for BE BDs Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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/openbmc/u-boot/board/freescale/ls1021atwr/ |
H A D | ls1021atwr.c | ebe4c1e6 Wed Aug 12 05:29:14 CDT 2015 Claudiu Manoil <claudiu.manoil@freescale.com> ls102xa: etsec: Use proper settings for BE BDs Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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/openbmc/u-boot/drivers/net/ |
H A D | tsec.c | ebe4c1e6 Wed Aug 12 05:29:14 CDT 2015 Claudiu Manoil <claudiu.manoil@freescale.com> ls102xa: etsec: Use proper settings for BE BDs Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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