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| /openbmc/linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-j7200-common-proc-board.dts | e38a45b0 Wed Sep 30 07:20:31 CDT 2020 Kishon Vijay Abraham I <kishon@ti.com> arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
e38a45b0 Wed Sep 30 07:20:31 CDT 2020 Kishon Vijay Abraham I <kishon@ti.com> arm64: dts: ti: k3-j7200-common-proc-board: Configure the SERDES lane function
First two lanes of SERDES is connected to PCIe, third lane is
connected to QSGMII and the last lane is connected to USB. However,
Cadence torrent SERDES doesn't support more than 2 protocols
at the same time. Configure it only for PCIe and QSGMII.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20200930122032.23481-6-rogerq@ti.com
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