Searched hist:e2842496 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/u-boot/drivers/serial/ |
| H A D | serial_sifive.c | e2842496 Sat Dec 15 00:05:15 CST 2018 Anup Patel <anup@brainfault.org> drivers: serial: Add SiFive UART driver
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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| H A D | Kconfig | e2842496 Sat Dec 15 00:05:15 CST 2018 Anup Patel <anup@brainfault.org> drivers: serial: Add SiFive UART driver
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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| H A D | Makefile | e2842496 Sat Dec 15 00:05:15 CST 2018 Anup Patel <anup@brainfault.org> drivers: serial: Add SiFive UART driver
This patch adds SiFive UART driver. The driver is 100% DM driver
and it determines input clock using clk framework.
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
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