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| /openbmc/linux/arch/arm64/boot/dts/hisilicon/ |
| H A D | hip05.dtsi | dbb58d0f Fri Jan 29 02:39:01 CST 2016 Kefeng Wang <wangkefeng.wang@huawei.com> arm64: dts: hip05: Add L2 cache topology
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
dbb58d0f Fri Jan 29 02:39:01 CST 2016 Kefeng Wang <wangkefeng.wang@huawei.com> arm64: dts: hip05: Add L2 cache topology
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
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