"d525d3d0" (history) in projects: openbmc

Searched hist:d525d3d0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/gpu/drm/aspeed/
H A D	aspeed_gfx_drv.c	d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com
H A D	aspeed_gfx.h	d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com d525d3d0 Tue Mar 01 20:49:28 CST 2022 Tommy Haung <tommy_huang@aspeedtech.com> drm/aspeed: Update INTR_STS handling Add interrupt clear register define for further chip support. OpenBMC-Staging-Count: 1 Signed-off-by: Tommy Haung <tommy_huang@aspeedtech.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://patchwork.freedesktop.org/patch/msgid/20220302024930.18758-4-tommy_huang@aspeedtech.com

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