Searched hist:cccbe3e5 (Results 1 – 3 of 3) sorted by relevance
/openbmc/linux/drivers/soc/qcom/ |
H A D | rpmh.c | cccbe3e5 Tue Oct 18 10:28:37 CDT 2022 Maulik Shah <quic_mkshah@quicinc.com> soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state.
To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state.
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
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H A D | rpmh-internal.h | cccbe3e5 Tue Oct 18 10:28:37 CDT 2022 Maulik Shah <quic_mkshah@quicinc.com> soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state.
To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state.
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
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H A D | rpmh-rsc.c | cccbe3e5 Tue Oct 18 10:28:37 CDT 2022 Maulik Shah <quic_mkshah@quicinc.com> soc: qcom: rpmh-rsc: Write CONTROL_TCS with next timer wakeup
The next wakeup timer value needs to be set in always on domain timer as the arch timer interrupt can not wakeup the SoC if after the deepest CPUidle states the SoC also enters deepest low power state.
To wakeup the SoC in such scenarios the earliest wakeup time is set in CONTROL_TCS and the firmware takes care of setting up its own timer in always on domain with next wakeup time. The timer wakes up the RSC and sets resources back to wake state.
Signed-off-by: Maulik Shah <quic_mkshah@quicinc.com> Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> # SM8450 Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20221018152837.619426-7-ulf.hansson@linaro.org
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