Searched hist:cc9d3fa2 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/drivers/staging/media/tegra-video/ |
| H A D | csi.h | cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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| H A D | tegra210.c | cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
|
| H A D | TODO | cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
|
| H A D | csi.c | cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
cc9d3fa2 Tue Aug 11 19:27:21 CDT 2020 Sowjanya Komatineni <skomatineni@nvidia.com> media: tegra-video: Compute settle times based on the clock rate
Settle time determines the number of cil clock cyles to wait after
LP00 when moving from LP to HS.
This patch computes T-CLK-SETTLE and T-HS-SETTLE times based on cil
clock rate and pixel rate from the sensor and programs them during
streaming.
T-CLK-SETTLE time is the interval during which receiver will ignore
any HS transitions on clock lane starting from the beginning of
T-CLK-PREPARE.
T-HS-SETTLE time is the interval during which recevier will ignore
any HS transitions on data lane starting from the beginning of
T-HS-PREPARE.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
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