Searched hist:cae88930 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/arm64/kvm/vgic/ |
| H A D | vgic-v3.c | cae88930 Sat May 14 05:25:24 CDT 2022 Marc Zyngier <maz@kernel.org> KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
original M1 and generate random SErrors in the host when a guest
tickles the GICv3 CPU interface the wrong way.
Add the part numbers for both the CPU types found in these two
new implementations, and add them to the hall of shame. This also
applies to the Ultra version, as it is composed of 2 Max SoCs.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220514102524.3188730-1-maz@kernel.org
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| /openbmc/linux/arch/arm64/include/asm/ |
| H A D | cputype.h | cae88930 Sat May 14 05:25:24 CDT 2022 Marc Zyngier <maz@kernel.org> KVM: arm64: vgic-v3: List M1 Pro/Max as requiring the SEIS workaround
Unsusprisingly, Apple M1 Pro/Max have the exact same defect as the
original M1 and generate random SErrors in the host when a guest
tickles the GICv3 CPU interface the wrong way.
Add the part numbers for both the CPU types found in these two
new implementations, and add them to the hall of shame. This also
applies to the Ultra version, as it is composed of 2 Max SoCs.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20220514102524.3188730-1-maz@kernel.org
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