Searched hist:c72f4d4c (Results 1 – 5 of 5) sorted by relevance
| /openbmc/u-boot/arch/arm/mach-uniphier/clk/ |
| H A D | pll-ld11.c | c72f4d4c Wed Sep 21 17:42:19 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| H A D | Makefile | c72f4d4c Wed Sep 21 17:42:19 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| /openbmc/u-boot/arch/arm/mach-uniphier/ |
| H A D | sc64-regs.h | c72f4d4c Wed Sep 21 17:42:19 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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| H A D | board_init.c | c72f4d4c Wed Sep 21 17:42:19 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
|
| H A D | init.h | c72f4d4c Wed Sep 21 17:42:19 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> ARM: uniphier: add PLL init code for LD11 SoC
- Initialize PLLs (SPL initializes only DPLL to save the precious
SPL memory footprint)
- Adjust CPLL/MPLL to the final tape-out frequency
- Set the Cortex-A53 clock to the maximum frequency since it is
running at 500MHz (SPLL/4) on startup
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
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