Searched hist:c3719bd9 (Results 1 – 3 of 3) sorted by relevance
/openbmc/linux/arch/riscv/kernel/ |
H A D | cacheinfo.c | c3719bd9 Wed Jan 04 12:30:24 CST 2023 Pierre Gondois <pierre.gondois@arm.com> cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation
RISC-V's implementation of init_of_cache_level() is following the Devicetree Specification v0.3 regarding caches, cf.: - s3.7.3 'Internal (L1) Cache Properties' - s3.8 'Multi-level and Shared Cache Nodes'
Allow reusing the implementation by moving it.
Also make 'levels', 'leaves' and 'level' unsigned int.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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/openbmc/linux/include/linux/ |
H A D | cacheinfo.h | c3719bd9 Wed Jan 04 12:30:24 CST 2023 Pierre Gondois <pierre.gondois@arm.com> cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation
RISC-V's implementation of init_of_cache_level() is following the Devicetree Specification v0.3 regarding caches, cf.: - s3.7.3 'Internal (L1) Cache Properties' - s3.8 'Multi-level and Shared Cache Nodes'
Allow reusing the implementation by moving it.
Also make 'levels', 'leaves' and 'level' unsigned int.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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/openbmc/linux/drivers/base/ |
H A D | cacheinfo.c | c3719bd9 Wed Jan 04 12:30:24 CST 2023 Pierre Gondois <pierre.gondois@arm.com> cacheinfo: Use RISC-V's init_cache_level() as generic OF implementation
RISC-V's implementation of init_of_cache_level() is following the Devicetree Specification v0.3 regarding caches, cf.: - s3.7.3 'Internal (L1) Cache Properties' - s3.8 'Multi-level and Shared Cache Nodes'
Allow reusing the implementation by moving it.
Also make 'levels', 'leaves' and 'level' unsigned int.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Link: https://lore.kernel.org/r/20230104183033.755668-2-pierre.gondois@arm.com Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
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