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/openbmc/qemu/target/loongarch/insn_trans/
H A Dtrans_branch.c.incc2b618a8 Tue Jan 17 18:32:38 CST 2023 Richard Henderson <richard.henderson@linaro.org> target/loongarch: Disassemble jirl properly

While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.

Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
/openbmc/qemu/target/loongarch/
H A Ddisas.cc2b618a8 Tue Jan 17 18:32:38 CST 2023 Richard Henderson <richard.henderson@linaro.org> target/loongarch: Disassemble jirl properly

While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.

Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
H A Dinsns.decodec2b618a8 Tue Jan 17 18:32:38 CST 2023 Richard Henderson <richard.henderson@linaro.org> target/loongarch: Disassemble jirl properly

While jirl shares the same instruction format as bne etc,
it is not assembled the same. In particular, rd is printed
first not second and the immediate is not pc-relative.

Decode into the arg_rr_i structure, which prints correctly.
This changes the "offs" member to "imm", to update translate.

Reviewed-by: WANG Xuerui <git@xen0n.name>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>