Searched hist:ba50fee6 (Results 1 – 2 of 2) sorted by relevance
/openbmc/u-boot/board/freescale/p2041rdb/ |
H A D | cpld.h | ba50fee6 Tue Sep 13 04:51:39 CDT 2011 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
H A D | cpld.c | ba50fee6 Tue Sep 13 04:51:39 CDT 2011 Shaohui Xie <Shaohui.Xie@freescale.com> powerpc/p2041rdb: update cpld reset command according to CPLD 2.0 CPLD 2.0 provides a new register which bit[0] is set to '1' will reset board with initializing the CPLD registers to default values. And add bit[6] of register at offset 0x5 to use to enable flash bank selection. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|