Searched hist:b97028b8 (Results 1 – 4 of 4) sorted by relevance
| /openbmc/qemu/tests/tcg/riscv64/ |
| H A D | semihost.ld | b97028b8 Sat Jun 04 18:10:02 CDT 2022 Richard Henderson <richard.henderson@linaro.org> target/riscv: Set env->bins in gen_exception_illegal
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | issue1060.S | b97028b8 Sat Jun 04 18:10:02 CDT 2022 Richard Henderson <richard.henderson@linaro.org> target/riscv: Set env->bins in gen_exception_illegal
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| H A D | Makefile.softmmu-target | b97028b8 Sat Jun 04 18:10:02 CDT 2022 Richard Henderson <richard.henderson@linaro.org> target/riscv: Set env->bins in gen_exception_illegal
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|
| /openbmc/qemu/target/riscv/ |
| H A D | translate.c | b97028b8 Sat Jun 04 18:10:02 CDT 2022 Richard Henderson <richard.henderson@linaro.org> target/riscv: Set env->bins in gen_exception_illegal
While we set env->bins when unwinding for ILLEGAL_INST,
from e.g. csrrw, we weren't setting it for immediately
illegal instructions.
Add a testcase for mtval via both exception paths.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1060
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220604231004.49990-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
|