Searched hist:b8c8a959 (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/riscv/include/uapi/asm/ |
| H A D | elf.h | b8c8a959 Wed Oct 17 19:59:05 CDT 2018 Jim Wilson <jimw@sifive.com> RISC-V: Add FP register ptrace support for gdb.
Add a variable and a macro to describe FP registers, assuming only D is
supported. FP code is conditional on CONFIG_FPU. The FP regs and FCSR
are copied separately to avoid copying struct padding. Tested by hand and
with the gdb testsuite.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
b8c8a959 Wed Oct 17 19:59:05 CDT 2018 Jim Wilson <jimw@sifive.com> RISC-V: Add FP register ptrace support for gdb.
Add a variable and a macro to describe FP registers, assuming only D is
supported. FP code is conditional on CONFIG_FPU. The FP regs and FCSR
are copied separately to avoid copying struct padding. Tested by hand and
with the gdb testsuite.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
|
| /openbmc/linux/arch/riscv/kernel/ |
| H A D | ptrace.c | b8c8a959 Wed Oct 17 19:59:05 CDT 2018 Jim Wilson <jimw@sifive.com> RISC-V: Add FP register ptrace support for gdb.
Add a variable and a macro to describe FP registers, assuming only D is
supported. FP code is conditional on CONFIG_FPU. The FP regs and FCSR
are copied separately to avoid copying struct padding. Tested by hand and
with the gdb testsuite.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
b8c8a959 Wed Oct 17 19:59:05 CDT 2018 Jim Wilson <jimw@sifive.com> RISC-V: Add FP register ptrace support for gdb.
Add a variable and a macro to describe FP registers, assuming only D is
supported. FP code is conditional on CONFIG_FPU. The FP regs and FCSR
are copied separately to avoid copying struct padding. Tested by hand and
with the gdb testsuite.
Signed-off-by: Jim Wilson <jimw@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
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