"b6768530" (history) in projects: openbmc

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/openbmc/linux/drivers/clk/renesas/
H A D	r9a07g043-cpg.c	`b6768530 Sun May 01 03:34:49 CDT 2022 Biju Das <biju.das.jz@bp.renesas.com> clk: renesas: r9a07g043: Add TSU clock and reset entry Add TSU clock and reset entry to CPG driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>`