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| /openbmc/u-boot/drivers/clk/rockchip/ |
| H A D | clk_rk3328.c | b375d841 Wed Sep 20 01:35:44 CDT 2017 David Wu <david.wu@rock-chips.com> rockchip: clk: Add rk3328 SARADC clock support
The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1).
SARADC integer divider control register is 10-bits width.
Signed-off-by: David Wu <david.wu@rock-chips.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
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