| H A D | symbol-elf.c | b2f76050 Sun Jun 04 19:34:09 CDT 2017 Li Bin <huawei.libin@huawei.com> perf symbols: Fix plt entry calculation for ARM and AARCH64
On x86, the plt header size is as same as the plt entry size, and can be
identified from shdr's sh_entsize of the plt.
But we can't assume that the sh_entsize of the plt shdr is always the
plt entry size in all architecture, and the plt header size may be not
as same as the plt entry size in some architecure.
On ARM, the plt header size is 20 bytes and the plt entry size is 12
bytes (don't consider the FOUR_WORD_PLT case) that refer to the binutils
implementation. The plt section is as follows:
Disassembly of section .plt:
000004a0 <__cxa_finalize@plt-0x14>:
4a0: e52de004 push {lr} ; (str lr, [sp, #-4]!)
4a4: e59fe004 ldr lr, [pc, #4] ; 4b0 <_init+0x1c>
4a8: e08fe00e add lr, pc, lr
4ac: e5bef008 ldr pc, [lr, #8]!
4b0: 00008424 .word 0x00008424
000004b4 <__cxa_finalize@plt>:
4b4: e28fc600 add ip, pc, #0, 12
4b8: e28cca08 add ip, ip, #8, 20 ; 0x8000
4bc: e5bcf424 ldr pc, [ip, #1060]! ; 0x424
000004c0 <printf@plt>:
4c0: e28fc600 add ip, pc, #0, 12
4c4: e28cca08 add ip, ip, #8, 20 ; 0x8000
4c8: e5bcf41c ldr pc, [ip, #1052]! ; 0x41c
On AARCH64, the plt header size is 32 bytes and the plt entry size is 16
bytes. The plt section is as follows:
Disassembly of section .plt:
0000000000000560 <__cxa_finalize@plt-0x20>:
560: a9bf7bf0 stp x16, x30, [sp,#-16]!
564: 90000090 adrp x16, 10000 <__FRAME_END__+0xf8a8>
568: f944be11 ldr x17, [x16,#2424]
56c: 9125e210 add x16, x16, #0x978
570: d61f0220 br x17
574: d503201f nop
578: d503201f nop
57c: d503201f nop
0000000000000580 <__cxa_finalize@plt>:
580: 90000090 adrp x16, 10000 <__FRAME_END__+0xf8a8>
584: f944c211 ldr x17, [x16,#2432]
588: 91260210 add x16, x16, #0x980
58c: d61f0220 br x17
0000000000000590 <__gmon_start__@plt>:
590: 90000090 adrp x16, 10000 <__FRAME_END__+0xf8a8>
594: f944c611 ldr x17, [x16,#2440]
598: 91262210 add x16, x16, #0x988
59c: d61f0220 br x17
NOTES:
In addition to ARM and AARCH64, other architectures, such as
s390/alpha/mips/parisc/poperpc/sh/sparc/xtensa also need to consider
this issue.
Signed-off-by: Li Bin <huawei.libin@huawei.com>
Acked-by: Namhyung Kim <namhyung@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexis Berlemont <alexis.berlemont@gmail.com>
Cc: David Tolnay <dtolnay@gmail.com>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Hemant Kumar <hemant@linux.vnet.ibm.com>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Wang Nan <wangnan0@huawei.com>
Cc: zhangmengting@huawei.com
Link: http://lkml.kernel.org/r/1496622849-21877-1-git-send-email-huawei.libin@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
b2f76050 Sun Jun 04 19:34:09 CDT 2017 Li Bin <huawei.libin@huawei.com> perf symbols: Fix plt entry calculation for ARM and AARCH64
On x86, the plt header size is as same as the plt entry size, and can be
identified from shdr's sh_entsize of the plt.
But we can't assume that the sh_entsize of the plt shdr is always the
plt entry size in all architecture, and the plt header size may be not
as same as the plt entry size in some architecure.
On ARM, the plt header size is 20 bytes and the plt entry size is 12
bytes (don't consider the FOUR_WORD_PLT case) that refer to the binutils
implementation. The plt section is as follows:
Disassembly of section .plt:
000004a0 <__cxa_finalize@plt-0x14>:
4a0: e52de004 push {lr} ; (str lr, [sp, #-4]!)
4a4: e59fe004 ldr lr, [pc, #4] ; 4b0 <_init+0x1c>
4a8: e08fe00e add lr, pc, lr
4ac: e5bef008 ldr pc, [lr, #8]!
4b0: 00008424 .word 0x00008424
000004b4 <__cxa_finalize@plt>:
4b4: e28fc600 add ip, pc, #0, 12
4b8: e28cca08 add ip, ip, #8, 20 ; 0x8000
4bc: e5bcf424 ldr pc, [ip, #1060]! ; 0x424
000004c0 <printf@plt>:
4c0: e28fc600 add ip, pc, #0, 12
4c4: e28cca08 add ip, ip, #8, 20 ; 0x8000
4c8: e5bcf41c ldr pc, [ip, #1052]! ; 0x41c
On AARCH64, the plt header size is 32 bytes and the plt entry size is 16
bytes. The plt section is as follows:
Disassembly of section .plt:
0000000000000560 <__cxa_finalize@plt-0x20>:
560: a9bf7bf0 stp x16, x30, [sp,#-16]!
564: 90000090 adrp x16, 10000 <__FRAME_END__+0xf8a8>
568: f944be11 ldr x17, [x16,#2424]
56c: 9125e210 add x16, x16, #0x978
570: d61f0220 br x17
574: d503201f nop
578: d503201f nop
57c: d503201f nop
0000000000000580 <__cxa_finalize@plt>:
580: 90000090 adrp x16, 10000 <__FRAME_END__+0xf8a8>
584: f944c211 ldr x17, [x16,#2432]
588: 91260210 add x16, x16, #0x980
58c: d61f0220 br x17
0000000000000590 <__gmon_start__@plt>:
590: 90000090 adrp x16, 10000 <__FRAME_END__+0xf8a8>
594: f944c611 ldr x17, [x16,#2440]
598: 91262210 add x16, x16, #0x988
59c: d61f0220 br x17
NOTES:
In addition to ARM and AARCH64, other architectures, such as
s390/alpha/mips/parisc/poperpc/sh/sparc/xtensa also need to consider
this issue.
Signed-off-by: Li Bin <huawei.libin@huawei.com>
Acked-by: Namhyung Kim <namhyung@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexis Berlemont <alexis.berlemont@gmail.com>
Cc: David Tolnay <dtolnay@gmail.com>
Cc: Hanjun Guo <guohanjun@huawei.com>
Cc: Hemant Kumar <hemant@linux.vnet.ibm.com>
Cc: Masami Hiramatsu <mhiramat@kernel.org>
Cc: Milian Wolff <milian.wolff@kdab.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Wang Nan <wangnan0@huawei.com>
Cc: zhangmengting@huawei.com
Link: http://lkml.kernel.org/r/1496622849-21877-1-git-send-email-huawei.libin@huawei.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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