Searched hist:b03a466d (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | p1021_serdes.c | b03a466d Tue Feb 01 09:55:58 CST 2011 Prabhakar Kushwaha <prabhakar@freescale.com> powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /openbmc/u-boot/drivers/pci/ |
| H A D | fsl_pci_init.c | b03a466d Tue Feb 01 09:55:58 CST 2011 Prabhakar Kushwaha <prabhakar@freescale.com> powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /openbmc/u-boot/include/ |
| H A D | pci.h | b03a466d Tue Feb 01 09:55:58 CST 2011 Prabhakar Kushwaha <prabhakar@freescale.com> powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | config_mpc85xx.h | b03a466d Tue Feb 01 09:55:58 CST 2011 Prabhakar Kushwaha <prabhakar@freescale.com> powerpc/85xx: Handle PCIe initialization requires for P1021 class SoCs
The P1011, P1012, P1015, P1016, P1020, P1021, P1024, & P1025 SoCs require
that we initialize the SERDES registers if the lanes are configured for
PCIe. Additionally these devices PCIe controller do not support ASPM
and we have to explicitly disable it.
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|