Searched hist:ae4a70c07196b76a67b772318b714ce910e10004 (Results 1 – 2 of 2) sorted by relevance
/openbmc/qemu/target/riscv/ |
H A D | gdbstub.c | ae4a70c07196b76a67b772318b714ce910e10004 Tue Jan 28 17:32:16 CST 2020 Keith Packard <keithp@keithp.com> riscv: Separate FPU register size from core register size in gdbstub [v2]
The size of the FPU registers is dictated by the 'f' and 'd' features, not the core processor register size. Processors with the 'd' feature have 64-bit FPU registers. Processors without the 'd' feature but with the 'f' feature have 32-bit FPU registers.
Signed-off-by: Keith Packard <keithp@keithp.com> [Palmer: This requires manually triggering a rebuild of riscv32-softmmu/gdbstub-xml.c] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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/openbmc/qemu/ |
H A D | configure | ae4a70c07196b76a67b772318b714ce910e10004 Tue Jan 28 17:32:16 CST 2020 Keith Packard <keithp@keithp.com> riscv: Separate FPU register size from core register size in gdbstub [v2]
The size of the FPU registers is dictated by the 'f' and 'd' features, not the core processor register size. Processors with the 'd' feature have 64-bit FPU registers. Processors without the 'd' feature but with the 'f' feature have 32-bit FPU registers.
Signed-off-by: Keith Packard <keithp@keithp.com> [Palmer: This requires manually triggering a rebuild of riscv32-softmmu/gdbstub-xml.c] Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
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