Searched hist:ae10ce93 (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/arm64/boot/dts/ti/ |
| H A D | k3-j7200.dtsi | ae10ce93 Wed Jan 20 13:51:45 CST 2021 Nishanth Menon <nm@ti.com> arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210120195145.32259-1-nm@ti.com
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| H A D | k3-am65.dtsi | ae10ce93 Wed Jan 20 13:51:45 CST 2021 Nishanth Menon <nm@ti.com> arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210120195145.32259-1-nm@ti.com
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| H A D | k3-j721e.dtsi | ae10ce93 Wed Jan 20 13:51:45 CST 2021 Nishanth Menon <nm@ti.com> arm64: dts: ti: k3*: Fixup PMU compatibility to be CPU specific
We can use CPU specific pmu configuration to expose the appropriate
CPU specific events rather than just the basic generic pmuv3 perf
events.
Reported-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Tested-by: Suman Anna <s-anna@ti.com>
Reviewed-by: Tero Kristo <kristo@kernel.org>
Link: https://lore.kernel.org/r/20210120195145.32259-1-nm@ti.com
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