Searched hist:a1559537 (Results 1 – 6 of 6) sorted by relevance
| /openbmc/qemu/target/hexagon/mmvec/ |
| H A D | mmvec.h | a1559537 Wed Mar 17 11:48:57 CDT 2021 Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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| /openbmc/qemu/target/hexagon/ |
| H A D | hex_arch_types.h | a1559537 Wed Mar 17 11:48:57 CDT 2021 Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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| H A D | internal.h | a1559537 Wed Mar 17 11:48:57 CDT 2021 Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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| H A D | insn.h | a1559537 Wed Mar 17 11:48:57 CDT 2021 Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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| H A D | cpu.h | a1559537 Wed Mar 17 11:48:57 CDT 2021 Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
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| H A D | cpu.c | a1559537 Wed Mar 17 11:48:57 CDT 2021 Taylor Simpson <tsimpson@quicinc.com> Hexagon HVX (target/hexagon) add Hexagon Vector eXtensions (HVX) to core
HVX is a set of wide vector instructions. Machine state includes
vector registers (VRegs)
vector predicate registers (QRegs)
temporary registers for intermediate values
store buffer (masked stores and scatter/gather)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
|