Searched hist:"9 c5a0a3a" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/mediatek/ |
| H A D | clk-mt2712-mm.c | 9c5a0a3a Wed Apr 01 15:17:34 CDT 2020 Enric Balletbo i Serra <enric.balletbo@collabora.com> clk / soc: mediatek: Bind clock and gpu driver for mt2712
Now that the mmsys driver is the top-level entry point for the
multimedia subsystem, we could bind the clock and the gpu driver on
those devices that is expected to work, so the drm driver is
intantiated by the mmsys driver and display, hopefully, working again on
those devices.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200401201736.2980433-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
9c5a0a3a Wed Apr 01 15:17:34 CDT 2020 Enric Balletbo i Serra <enric.balletbo@collabora.com> clk / soc: mediatek: Bind clock and gpu driver for mt2712
Now that the mmsys driver is the top-level entry point for the
multimedia subsystem, we could bind the clock and the gpu driver on
those devices that is expected to work, so the drm driver is
intantiated by the mmsys driver and display, hopefully, working again on
those devices.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200401201736.2980433-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
|
| /openbmc/linux/drivers/soc/mediatek/ |
| H A D | mtk-mmsys.c | 9c5a0a3a Wed Apr 01 15:17:34 CDT 2020 Enric Balletbo i Serra <enric.balletbo@collabora.com> clk / soc: mediatek: Bind clock and gpu driver for mt2712
Now that the mmsys driver is the top-level entry point for the
multimedia subsystem, we could bind the clock and the gpu driver on
those devices that is expected to work, so the drm driver is
intantiated by the mmsys driver and display, hopefully, working again on
those devices.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200401201736.2980433-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
9c5a0a3a Wed Apr 01 15:17:34 CDT 2020 Enric Balletbo i Serra <enric.balletbo@collabora.com> clk / soc: mediatek: Bind clock and gpu driver for mt2712
Now that the mmsys driver is the top-level entry point for the
multimedia subsystem, we could bind the clock and the gpu driver on
those devices that is expected to work, so the drm driver is
intantiated by the mmsys driver and display, hopefully, working again on
those devices.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20200401201736.2980433-2-enric.balletbo@collabora.com
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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