Searched hist:"99 d451a7" (Results 1 – 3 of 3) sorted by relevance
| /openbmc/linux/arch/riscv/boot/dts/microchip/ |
| H A D | mpfs-polarberry-fabric.dtsi | 99d451a7 Tue Sep 27 06:19:17 CDT 2022 Conor Dooley <conor.dooley@microchip.com> riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
In today's edition of moving things around:
The PCIe root port on PolarFire SoC is more part of the FPGA than of
the Core Complex. It is located on the other side of the chip and,
apart from its interrupts, most of its configuration is determined
by the FPGA bitstream rather. This includes:
- address translation in both directions
- the addresses at which the config and data regions appear to the
core complex
- the clocks used by the AXI bus
- the plic interrupt used
Moving the PCIe node to the -fabric.dtsi makes it clearer than a
singular configuration for root port is not correct & allows the
base SoC dtsi to be more easily included.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
| H A D | mpfs-icicle-kit-fabric.dtsi | 99d451a7 Tue Sep 27 06:19:17 CDT 2022 Conor Dooley <conor.dooley@microchip.com> riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
In today's edition of moving things around:
The PCIe root port on PolarFire SoC is more part of the FPGA than of
the Core Complex. It is located on the other side of the chip and,
apart from its interrupts, most of its configuration is determined
by the FPGA bitstream rather. This includes:
- address translation in both directions
- the addresses at which the config and data regions appear to the
core complex
- the clocks used by the AXI bus
- the plic interrupt used
Moving the PCIe node to the -fabric.dtsi makes it clearer than a
singular configuration for root port is not correct & allows the
base SoC dtsi to be more easily included.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|
| H A D | mpfs.dtsi | 99d451a7 Tue Sep 27 06:19:17 CDT 2022 Conor Dooley <conor.dooley@microchip.com> riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi
In today's edition of moving things around:
The PCIe root port on PolarFire SoC is more part of the FPGA than of
the Core Complex. It is located on the other side of the chip and,
apart from its interrupts, most of its configuration is determined
by the FPGA bitstream rather. This includes:
- address translation in both directions
- the addresses at which the config and data regions appear to the
core complex
- the clocks used by the AXI bus
- the plic interrupt used
Moving the PCIe node to the -fabric.dtsi makes it clearer than a
singular configuration for root port is not correct & allows the
base SoC dtsi to be more easily included.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
|