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| H A D | tegra194.dtsi | 939e7430 Fri Jul 26 05:16:18 CDT 2019 Thierry Reding <treding@nvidia.com> arm64: tegra: Fix base address for SOR1 on Tegra194
The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
939e7430 Fri Jul 26 05:16:18 CDT 2019 Thierry Reding <treding@nvidia.com> arm64: tegra: Fix base address for SOR1 on Tegra194
The SOR1 hardware block's registers start at physical address 0x15b40000
as correctly specified by the unit-address, but the reg property lists a
wrong value, likely because it was copy-and-pasted from SOR0 but not
correctly updated.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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