Searched hist:91143873 (Results 1 – 5 of 5) sorted by relevance
| /openbmc/linux/drivers/gpu/drm/msm/disp/dpu1/ |
| H A D | dpu_hw_intf.c | 4ae0cd31 Wed Dec 13 15:30:17 CST 2023 Jessica Zhang <quic_jesszhan@quicinc.com> drm/msm/dpu: Set input_sel bit for INTF
[ Upstream commit 980fffd0c69e5df0f67ee089d405899d532aeeab ]
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark <robdclark@gmail.com>
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/572007/
Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
d80d7f89 Wed Apr 26 17:37:24 CDT 2023 Marijn Suijten <marijn.suijten@somainline.org> drm/msm/dpu: Sort INTF registers numerically
A bunch of registers were appended at the end in e.g. commit
91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
rather than being inserted in a place that maintains numerical sorting:
restore said numerical sorting.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/534213/
Link: https://lore.kernel.org/r/20230411-dpu-intf-te-v4-10-27ce1a5ab5c6@somainline.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
91143873 Wed Jun 22 12:18:34 CDT 2022 Jessica Zhang <quic_jesszhan@quicinc.com> drm/msm/dpu: Add MISR register support for interface
Add support for setting MISR registers within the interface
Changes since V1:
- Replaced dpu_hw_intf collect_misr and setup_misr implementations with
calls to dpu_hw_utils helper methods
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490730/
Link: https://lore.kernel.org/r/20220622171835.7558-4-quic_jesszhan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
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| H A D | dpu_hw_util.c | 4ae0cd31 Wed Dec 13 15:30:17 CST 2023 Jessica Zhang <quic_jesszhan@quicinc.com> drm/msm/dpu: Set input_sel bit for INTF
[ Upstream commit 980fffd0c69e5df0f67ee089d405899d532aeeab ]
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark <robdclark@gmail.com>
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/572007/
Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
| H A D | dpu_hw_util.h | 4ae0cd31 Wed Dec 13 15:30:17 CST 2023 Jessica Zhang <quic_jesszhan@quicinc.com> drm/msm/dpu: Set input_sel bit for INTF
[ Upstream commit 980fffd0c69e5df0f67ee089d405899d532aeeab ]
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark <robdclark@gmail.com>
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/572007/
Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
|
| H A D | dpu_hw_intf.h | 91143873 Wed Jun 22 12:18:34 CDT 2022 Jessica Zhang <quic_jesszhan@quicinc.com> drm/msm/dpu: Add MISR register support for interface
Add support for setting MISR registers within the interface
Changes since V1:
- Replaced dpu_hw_intf collect_misr and setup_misr implementations with
calls to dpu_hw_utils helper methods
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/490730/
Link: https://lore.kernel.org/r/20220622171835.7558-4-quic_jesszhan@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
|
| H A D | dpu_hw_lm.c | 4ae0cd31 Wed Dec 13 15:30:17 CST 2023 Jessica Zhang <quic_jesszhan@quicinc.com> drm/msm/dpu: Set input_sel bit for INTF
[ Upstream commit 980fffd0c69e5df0f67ee089d405899d532aeeab ]
Set the input_sel bit for encoders as it was missed in the initial
implementation.
Reported-by: Rob Clark <robdclark@gmail.com>
Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39
Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface")
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Patchwork: https://patchwork.freedesktop.org/patch/572007/
Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
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