Searched hist:"910 a17e5" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/arm/include/asm/ |
| H A D | cache.h | 910a17e5 Tue Sep 15 04:23:53 CDT 2009 Kirill A. Shutemov <kirill@shutemov.name> ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.
List of CPUs with cache line size != 32 should be expanded later.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
910a17e5 Tue Sep 15 04:23:53 CDT 2009 Kirill A. Shutemov <kirill@shutemov.name> ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.
List of CPUs with cache line size != 32 should be expanded later.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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| /openbmc/linux/arch/arm/mm/ |
| H A D | Kconfig | 910a17e5 Tue Sep 15 04:23:53 CDT 2009 Kirill A. Shutemov <kirill@shutemov.name> ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.
List of CPUs with cache line size != 32 should be expanded later.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
910a17e5 Tue Sep 15 04:23:53 CDT 2009 Kirill A. Shutemov <kirill@shutemov.name> ARM: 5700/1: ARM: Introduce ARM_L1_CACHE_SHIFT to define cache line size
Currently kernel believes that all ARM CPUs have L1_CACHE_SHIFT == 5.
It's not true at least for CPUs based on Cortex-A8.
List of CPUs with cache line size != 32 should be expanded later.
Signed-off-by: Kirill A. Shutemov <kirill@shutemov.name>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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