Home
last modified time | relevance | path

Searched hist:"8 c80c99f" (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/target/i386/
H A Dcpu.h8c80c99f Thu Jul 05 04:09:54 CDT 2018 Robert Hoo <robert.hu@linux.intel.com> i386: Add new MSR indices for IA32_PRED_CMD and IA32_ARCH_CAPABILITIES

IA32_PRED_CMD MSR gives software a way to issue commands that affect the state
of indirect branch predictors. Enumerated by CPUID.(EAX=7H,ECX=0):EDX[26].
IA32_ARCH_CAPABILITIES MSR enumerates architectural features of RDCL_NO and
IBRS_ALL. Enumerated by CPUID.(EAX=07H, ECX=0):EDX[29].

https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf

Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
Message-Id: <1530781798-183214-2-git-send-email-robert.hu@linux.intel.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>