Searched hist:"89683 fde" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/sound/soc/codecs/ |
| H A D | tas2552.h | 89683fde Thu Jun 04 08:04:16 CDT 2015 Peter Ujfalusi <peter.ujfalusi@ti.com> ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.
The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
89683fde Thu Jun 04 08:04:16 CDT 2015 Peter Ujfalusi <peter.ujfalusi@ti.com> ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.
The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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| H A D | tas2552.c | 89683fde Thu Jun 04 08:04:16 CDT 2015 Peter Ujfalusi <peter.ujfalusi@ti.com> ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.
The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
89683fde Thu Jun 04 08:04:16 CDT 2015 Peter Ujfalusi <peter.ujfalusi@ti.com> ASoC: tas2552: Correct PDM configuration register bit definitions
The PDM clock can be selected via bit0-1.
PDM_DATA_ES bit is at bit2.
The code were trying to select BCLK as PDM reference clock but instead
it was selecting PLL and set the DATA_ES bit to 1.
Selecting the PLL output as reference clock as default does make sense,
but the driver should not change the PDM data edge.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
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