Searched hist:"87 d0bab2" (Results 1 – 4 of 4) sorted by relevance
/openbmc/linux/drivers/amba/ |
H A D | Makefile | 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture.
The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus.
Some of configuration params could be passed from DT too if needed.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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H A D | tegra-ahb.c | 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture.
The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus.
Some of configuration params could be passed from DT too if needed.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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/openbmc/linux/arch/arm/mach-tegra/ |
H A D | Kconfig | 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture.
The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus.
Some of configuration params could be passed from DT too if needed.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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/openbmc/linux/drivers/ |
H A D | Makefile | 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture.
The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus.
Some of configuration params could be passed from DT too if needed.
Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> 87d0bab2 Mon May 07 05:24:48 CDT 2012 Hiroshi DOYU <hdoyu@nvidia.com> ARM: tegra: Add Tegra AHB driver Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <hdoyu@nvidia.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Stephen Warren <swarren@nvidia.com>
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