Searched hist:"83 fb5b55" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/arm64/boot/dts/apple/ |
| H A D | t600x-common.dtsi | 83fb5b55 Tue Nov 22 16:06:20 CST 2022 Rob Herring <robh@kernel.org> arm64: dts: apple: Add t600x L1/L2 cache properties and nodes
The t600x CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be described in
DT. The OS scheduler can make use of this information for scheduling
decisions.
The cache size information is based on various articles about the
processors. There's also an L3 system level cache (SLC). It's not
described here because SLCs typically have some MMIO interface which
would need to be described.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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| H A D | t6002.dtsi | 83fb5b55 Tue Nov 22 16:06:20 CST 2022 Rob Herring <robh@kernel.org> arm64: dts: apple: Add t600x L1/L2 cache properties and nodes
The t600x CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be described in
DT. The OS scheduler can make use of this information for scheduling
decisions.
The cache size information is based on various articles about the
processors. There's also an L3 system level cache (SLC). It's not
described here because SLCs typically have some MMIO interface which
would need to be described.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>
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