Searched hist:"8127 f46a" (Results 1 – 2 of 2) sorted by relevance
/openbmc/qemu/target/arm/tcg/ |
H A D | a64.decode | 8127f46a Fri May 12 09:40:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> target/arm: Convert Logical (immediate) to decodetree
Convert the ADD, ORR, EOR, ANDS (immediate) instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org [PMM: rebased] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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H A D | translate-a64.c | 8127f46a Fri May 12 09:40:55 CDT 2023 Richard Henderson <richard.henderson@linaro.org> target/arm: Convert Logical (immediate) to decodetree
Convert the ADD, ORR, EOR, ANDS (immediate) instructions.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20230512144106.3608981-10-peter.maydell@linaro.org [PMM: rebased] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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