Searched hist:"8069821 f" (Results 1 – 3 of 3) sorted by relevance
/openbmc/u-boot/arch/arm/cpu/armv8/ |
H A D | fwcall.c | 8069821f Tue Aug 16 14:08:48 CDT 2016 Alexander Graf <agraf@suse.de> arm: Provide common PSCI based reset handler Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
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H A D | Kconfig | 8069821f Tue Aug 16 14:08:48 CDT 2016 Alexander Graf <agraf@suse.de> arm: Provide common PSCI based reset handler Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
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/openbmc/u-boot/board/xilinx/zynqmp/ |
H A D | zynqmp.c | 8069821f Tue Aug 16 14:08:48 CDT 2016 Alexander Graf <agraf@suse.de> arm: Provide common PSCI based reset handler Most armv8 systems have PSCI support enabled in EL3, either through ARM Trusted Firmware or other firmware. On these systems, we do not need to implement system reset manually, but can instead rely on higher level firmware to deal with it. The exclude list seems excessive right now, but NXP is working on providing an in-tree PSCI implementation, so that all NXP systems can eventually use PSCI as well. Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: fix meson] Reviewed-by: Simon Glass <sjg@chromium.org>
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