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| H A D | xilinx_dma.txt | 7cb1e575 Tue Oct 22 12:00:19 CDT 2019 Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP
Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access
(AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory
access between memory and AXI4-Stream target peripherals. The AXI MCDMA
core provides a scatter-gather interface with multiple channel support
with independent configuration.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1571763622-29281-4-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
7cb1e575 Tue Oct 22 12:00:19 CDT 2019 Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> dt-bindings: dmaengine: xilinx_dma: Add binding for Xilinx MCDMA IP
Add devicetree binding for Xilinx AXI Multichannel Direct Memory Access
(AXI MCDMA) IP. The AXI MCDMA provides high-bandwidth direct memory
access between memory and AXI4-Stream target peripherals. The AXI MCDMA
core provides a scatter-gather interface with multiple channel support
with independent configuration.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/1571763622-29281-4-git-send-email-radhey.shyam.pandey@xilinx.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
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