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H A Dfsl_utils.h7bad8125 Fri Jul 01 04:32:36 CDT 2022 Shengjiu Wang <shengjiu.wang@nxp.com> ASoC: fsl_utils: Add function to handle PLL clock source

i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.
Add common function in fsl_utils to handle these two PLL
clock source, which are needed by CPU DAI drivers

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1656667961-1799-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
H A Dfsl_utils.c7bad8125 Fri Jul 01 04:32:36 CDT 2022 Shengjiu Wang <shengjiu.wang@nxp.com> ASoC: fsl_utils: Add function to handle PLL clock source

i.MX8MQ/MN/MM/MP platforms typically have 2 AUDIO PLLs being
configured to handle 8kHz and 11kHz series audio rates.
Add common function in fsl_utils to handle these two PLL
clock source, which are needed by CPU DAI drivers

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Link: https://lore.kernel.org/r/1656667961-1799-2-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>