Searched hist:"7 a6fca87" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/clk/sunxi/ |
| H A D | clk-sun9i-mmc.c | 7a6fca87 Tue Jan 20 09:46:31 CST 2015 Chen-Yu Tsai <wens@csie.org> clk: sunxi: Add driver for A80 MMC config clocks/resets
On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.
This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7a6fca87 Tue Jan 20 09:46:31 CST 2015 Chen-Yu Tsai <wens@csie.org> clk: sunxi: Add driver for A80 MMC config clocks/resets
On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.
This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|
| H A D | Makefile | 7a6fca87 Tue Jan 20 09:46:31 CST 2015 Chen-Yu Tsai <wens@csie.org> clk: sunxi: Add driver for A80 MMC config clocks/resets
On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.
This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
7a6fca87 Tue Jan 20 09:46:31 CST 2015 Chen-Yu Tsai <wens@csie.org> clk: sunxi: Add driver for A80 MMC config clocks/resets
On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.
This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
|