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| H A D | io.h | 7629a9f6 Fri Oct 26 12:42:08 CDT 2012 Will Deacon <will.deacon@arm.com> ARM: 7567/1: io: avoid GCC's offsettable addressing modes for halfword accesses
Using the 'o' memory constraint in inline assembly can result in GCC
generating invalid immediate offsets for memory access instructions with
reduced addressing capabilities (i.e. smaller than 12-bit immediate
offsets):
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54983
As there is no constraint to specify the exact addressing mode we need,
fallback to using 'Q' exclusively for halfword I/O accesses. This may
emit an additional add instruction (using an extra register) in order
to construct the address but it will always be accepted by GAS.
Reported-by: Bastian Hecht <hechtb@googlemail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
7629a9f6 Fri Oct 26 12:42:08 CDT 2012 Will Deacon <will.deacon@arm.com> ARM: 7567/1: io: avoid GCC's offsettable addressing modes for halfword accesses
Using the 'o' memory constraint in inline assembly can result in GCC
generating invalid immediate offsets for memory access instructions with
reduced addressing capabilities (i.e. smaller than 12-bit immediate
offsets):
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=54983
As there is no constraint to specify the exact addressing mode we need,
fallback to using 'Q' exclusively for halfword I/O accesses. This may
emit an additional add instruction (using an extra register) in order
to construct the address but it will always be accepted by GAS.
Reported-by: Bastian Hecht <hechtb@googlemail.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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