Searched hist:"72 e5706a" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/drivers/pinctrl/uniphier/ |
| H A D | pinctrl-uniphier.h | 72e5706a Tue May 31 03:05:14 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> pinctrl: uniphier: support 3-bit drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
72e5706a Tue May 31 03:05:14 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> pinctrl: uniphier: support 3-bit drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
|
| H A D | pinctrl-uniphier-core.c | 72e5706a Tue May 31 03:05:14 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> pinctrl: uniphier: support 3-bit drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
72e5706a Tue May 31 03:05:14 CDT 2016 Masahiro Yamada <yamada.masahiro@socionext.com> pinctrl: uniphier: support 3-bit drive strength control
The new ARMv8 SoC, PH1-LD20, supports more fine-grained drive
strength control. Drive strength of some pins are controlled by
3-bit width registers (8-level granularity).
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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