Searched hist:"6 d06fc4e" (Results 1 – 1 of 1) sorted by relevance
/openbmc/linux/drivers/clk/renesas/ |
H A D | r9a07g043-cpg.c | 6d06fc4e Wed Apr 03 15:09:52 CDT 2024 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org> 6d06fc4e Wed Apr 03 15:09:52 CDT 2024 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org> 6d06fc4e Wed Apr 03 15:09:52 CDT 2024 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org> 6d06fc4e Wed Apr 03 15:09:52 CDT 2024 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org> 6d06fc4e Wed Apr 03 15:09:52 CDT 2024 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org> 6d06fc4e Wed Apr 03 15:09:52 CDT 2024 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org> 6d06fc4e Wed Apr 03 15:09:52 CDT 2024 Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> clk: renesas: r9a07g043: Add clock and reset entry for PLIC
[ Upstream commit 44019387fce230beda35b83da3a2c9fc5787704e ]
Add the missing clock and reset entry for PLIC. Also add R9A07G043_NCEPLIC_ACLK to the critical clocks list.
Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20240403200952.633084-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
|