Searched hist:"6 bfe3fff" (Results 1 – 4 of 4) sorted by relevance
| /openbmc/u-boot/arch/arm/dts/ |
| H A D | zynq-dlc20-rev1.0.dts | 6bfe3fff Thu Sep 13 01:44:02 CDT 2018 Michal Simek <michal.simek@xilinx.com> arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).
Boards have mix of Winbond/ST QSPIs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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| H A D | Makefile | 6bfe3fff Thu Sep 13 01:44:02 CDT 2018 Michal Simek <michal.simek@xilinx.com> arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).
Boards have mix of Winbond/ST QSPIs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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| /openbmc/u-boot/board/xilinx/zynq/zynq-dlc20-rev1.0/ |
| H A D | ps7_init_gpl.c | 6bfe3fff Thu Sep 13 01:44:02 CDT 2018 Michal Simek <michal.simek@xilinx.com> arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).
Boards have mix of Winbond/ST QSPIs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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| /openbmc/u-boot/configs/ |
| H A D | zynq_dlc20_rev1_0_defconfig | 6bfe3fff Thu Sep 13 01:44:02 CDT 2018 Michal Simek <michal.simek@xilinx.com> arm: zynq: Add support for DLC20 board
Xilinx DLC20 has I2C0 with EEPROM(1KB), UART1, GPIO, SD0 (EMMC 4GB),
USB0 device, ENET0, QSPI (16MB) and DDR(two of 256MB each).
Boards have mix of Winbond/ST QSPIs.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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