Searched hist:"6 a4ccd9a" (Results 1 – 2 of 2) sorted by relevance
| /openbmc/linux/arch/arm/mach-meson/ |
| H A D | meson.c | 6a4ccd9a Tue Nov 18 08:25:41 CST 2014 Beniamino Galvani <b.galvani@gmail.com> ARM: meson: enable L2 cache
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
6a4ccd9a Tue Nov 18 08:25:41 CST 2014 Beniamino Galvani <b.galvani@gmail.com> ARM: meson: enable L2 cache
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
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| H A D | Kconfig | 6a4ccd9a Tue Nov 18 08:25:41 CST 2014 Beniamino Galvani <b.galvani@gmail.com> ARM: meson: enable L2 cache
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
6a4ccd9a Tue Nov 18 08:25:41 CST 2014 Beniamino Galvani <b.galvani@gmail.com> ARM: meson: enable L2 cache
This enables the L2 cache controller available in Amlogic SoCs.
Signed-off-by: Beniamino Galvani <b.galvani@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Carlo Caione <carlo@caione.org>
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